1. Field of the Invention
The present invention relates to a resistive switching memory, i.e., a resistive random access memory (RRAM) device, and more particularly to a resistive random access memory device embedding a tunnel insulating layer and a memory array using the same and fabrication method thereof.
2. Description of the Related Art
Today, NAND flash memory technology leads the markets of mass storage devices by scaling down continuously. However, since the size of device is scaled down below 20 nm, some reliability problems are recently coming out. Thus, various next generation non-volatile memories have been suggested and studied actively for replacing the NAND flash memory technology.
Among them, RRAM having a simple structure is advantageous for scaling down and basically has a material composition of MIM (metal-insulator-metal) as shown in FIG. 1. The switching operation of RRAM is divided into 3 steps. As shown in FIG. 2, it is consisted of a forming process that forms conductive filaments in an initial state to be a low resistance state, a reset operation that cuts off the conductive filaments to increase the resistance and a set operation that reproduce the conductive filaments to decrease the resistance. The forming process is an initial operation of the set operation and needs higher voltage than the others.
In the conventional structure of RRAM, because the interface between a metal and an insulator is plane, when voltages are applied to both ends, the electric field is uniformly distributed. So, in the MIM structure, because the conductive filaments produced during the forming and set operations are formed at random places, it is difficult to precisely control and shows a high reset current. Especially, a unipolar RRAM that operates as shown in FIG. 3(A) is disadvantageous in commercialization due to uneven switching parameter distribution and high reset current. Thus, recently, a bipolar RRAM that operates as shown in FIG. 3(B) is more interested.
In a memory array using RRAM, there is an array method, as shown in FIG. 4, that top and bottom electrodes are vertically crossed to each other to use as word and bit lines, respectively. For reading data, a V/2 method is used. Namely, as shown in FIG. 4, when a cell 300 is selected to be read, V and 0 voltages are applied to a bit line 200 as a top electrode and a word line 100 as a bottom electrode, respectively. And 1/2 V is applied to the other lines for applying only 1/2 V between the top and bottom electrodes of cells 410, 420, 430 and 440 commonly connected to each of the lines 100 and 200 of the cell 300 selected to be read. However, when the cell 300 selected to be read is FIRS (high resistance state), because not only a current (as a solid line shown in FIG. 4) of the selected cell, but also leakage currents (as broken lines shown in FIG. 4) of the adjacent cells 430 and 440 are sensed together, the leakage currents of the adjacent cells 430 and 440 are to be causes of an error in a reading operation and a restriction in an array size.
To overcome the leakage current problems of the adjacent cells, as shown in FIG. 5, it is operated as the V/2 method after changing the electrical property of a memory device by connecting each bipolar RRAM cell with a bipolar selector. Accordingly, because an additional process is needed to form the additional bipolar selectors, the complexity of the fabricating process is increased and the thickness of the entire device is thickly increased. So, there is a disadvantage in forming a high integration.
To overcome the above disadvantage, Korean Patent No. 10-1257365 discloses an attempt to simultaneously form a resistance change layer and a threshold switching layer for substituting a switching device. According the above patent, the bottom electrode is formed of platinum (Pt), the top electrode is formed of transition metal such as tungsten (W), a phase-change layer between the electrodes is formed of transition metal oxide such as niobium oxide (Nb2O6-x), vanadium oxide (V2O6-x) or Ti, Fe, Ni, etc. When oxygen ions within the phase-change layer are moved to the top electrode by applying a voltage to both electrodes, from the bottom electrode, the phase-change layer is materially changed into a state with oxygen vacancies to grow and form the threshold switching layer having a conductive property induced by heat energy in case of applying a higher voltage than the predetermined voltage and, in the top electrode, the resistance change layer is formed by oxidation reaction. Thus, it has techanical features simultaneously forming two layers having different characteristics each other by a single forming process.
However, because the Patent No. 10-1257365 also discloses the conventional MIM structure that is consisted of the bottom electrode formed of platinum (Pt), the top electrode formed of transition metal such as tungsten (W), the transition metal oxide filled between the electrodes and the threshold switching and resistance change layers formed by removing oxygen ions induced by applying a voltage to both electrodes, it is difficult to embody a three dimensional vertical array and also it needs an additional fabricating process separated from the process for adjacent circuit devices of the array. Namely, it is not compatible to the conventional silicon process.